KCCS
Precision Timing
High-performance phase-locked oscillator with ultra-low phase noise and excellent stability. 10-100 MHz, +/-0.5 ppb.
| Model | Package (mm) | Output | Supply | Temp. Range | Temp. Stability | Aging/Year | Phase Noise @10MHz (Typ) | Phase Noise @100MHz (Typ) | Freq. Range |
|---|---|---|---|---|---|---|---|---|---|
| KPLO38 | DIP 38×38×13 | Sine/CMOS | 3.3V/5V/12V | -40~+85℃ / -55~+105℃ | ≤±1 ppb | ≤±20 ppb | 10Hz:-130, 100Hz:-145, 1kHz:-160, 10kHz:-165, 100kHz:-165 dBc/Hz | — | 5~200 MHz |
| KPLO50 | DIP 50.8×50.8×19 | Sine/CMOS | 3.3V/5V/12V | -20~+70℃ | ≤±50 ppb | ≤±0.05 ppm | 1kHz: -162 dBc/Hz | 1kHz: -162 dBc/Hz | 10~400 MHz |
| KPLO25 | DIP 25.4×25.4×13 | Sine/CMOS | 3.3V/5V/12V | -40~+85℃ / -55~+105℃ | ≤±1 ppb | ≤±20 ppb | — | — | 5~200 MHz |
| KPLOSMA45 | SMA 60×45×16 | Sine/CMOS | 3.3V/5V/12V | -40~+85℃ / -55~+105℃ | ≤±0.2 ppb | ≤±20 ppb | @25MHz: 10Hz:-130, 100Hz:-145, 1kHz:-160, 10kHz:-175, 100kHz:-175, 1MHz:-175 dBc/Hz | — | 5~130 MHz |
A phase-locked oscillator (PLO) uses a phase-locked loop (PLL) to lock a high-performance VCO/OCXO to an external frequency reference (typically 10 MHz). This combines the low phase noise of a high-quality oscillator with the frequency accuracy and stability of the reference.
A PLO inherits the long-term accuracy and aging characteristics of its reference source while delivering the low phase noise and short-term stability of a premium VCO. KCCS PLOs achieve +/-0.5 ppb stability, <100 ms lock time, and outputs from 10 to 100 MHz.
Our technical team can help you choose the optimal oscillator for your specific application requirements.